1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit of the bonding option type which includes a function determination circuit for providing a different function to the semiconductor integrated circuit in a manufacturing process depending upon whether or not a bonding pad is bonded.
2. Description of the Related Art
In recent years, it is a common practice in the manufacturing of a semiconductor integrated circuit (hereinafter referred to as LSI) to perform manufacturing processes, as it is called pre-processes, prior to the assembling of the LSI, on the same chips, following which functions of the LSI are provided using the function determination circuit in order to produce different types of LSIs at a low cost. The determination of types by such manufacturing processes as described above is called a bonding option. FIG. 1 shows a circuit diagram of a conventional function determination circuit of a bonding option of LSI. Referring to FIG. 1, the circuit shown is a function determination circuit of the ground bonding option type and includes a bonding pad 1, pMOS transistor QP1 interconnecting the bonding pad 1 and a power supply line (voltage=VDD) 2 and connected at a gate electrode thereof to a ground line 3, CMOS invertor 4A having an input terminal connected to a drain electrode (junction A) of the transistor QP1, pMOS transistor QP2 whose gate electrode is connected to an output terminal (junction B) of an invertor 4A and whose drain electrode is connected to the junction A, and invertor 4B having an input terminal connected to the output terminal of the invertor 4A. In an LSI of the ground bonding option type which employs the circuit shown in FIG. 1, function determination is performed in the following manner in manufacturing processes.
First, when the bonding pad 1 is not bonded (non-bonding) to an external terminal of the LSI, electric charge is supplied from the power supply line 2 to the junction A via the transistor QP1 to raise voltage at the junction A. When the voltage at the junction A reaches a threshold level of the invertor 4A, the junction B is pulled down to the ground potential by the invertor 4A. Consequently, transistor QP2 is put into an ON-state, and the junction A is charged up to the level of power supply voltage VDD. As a result of a sequence of operations as described above, supply of charge through the transistors QP1 and QP2 is suspended, and the output φ1 of the function determination circuit exhibits a high level (H). A signal processing circuit (not shown) on a chip acts in response to a signal φ1 of the high level, so that the LSI will be given a function which is controlled under condition of φ1=H. At the time of this non-bonding, no current consumption occurs.
Next, function determination in the case that the bonding pad 1 is bonded (ground bonding) to the external terminal 5 for grounding the LSI will be described. In this instance, charge is supplied to the junction A through transistors QP1 and QP2. However, since both the transistors have a low current capacity, voltage at junction A exhibits ground potential. Consequently, a junction B, which is an output point of invertor 4A, exhibits a power supply voltage VDD level, and the transistor QP2 is put into an OFF-state. In this instance, output φ1 of the function determination circuit exhibits a low level (L). As a result of the operations described above, this LSI will be given a function which is controlled under conditions of φ1=L. In the case of the ground bonding current always flows to the bonding pad 1 through transistor QP1, resulting in generation of consumption current of the function determination circuit.
It is to be noted that, from the foregoing description of operation, it can be seen that the elements which is directly related to the bonding option in the function determination circuit are the bonding pad 1 and pMOS transistor QP1. The circuit comprising the invertor 4A and transistor QP2 acts as a latch to hold the state at the junction A thereby to make the operation of the circuit surer. Meanwhile, the invertor 4B acts as a buffer for a load, that is, the signal processing circuit.
FIG. 2 is a circuit diagram of another example of a conventional function determination circuit. The circuit shown is a function determination circuit of the power supply bonding option type. Referring to FIG. 2, in the circuit shown, charge is pulled down to a ground line 3 from a bonding pad 1 (junction C) through nMOS transistors QN1 and QN2. From this, although phases of the junctions C and D are reverse to the phases in the function determination circuit of the ground bonding option type, other principles of operation are the same as in the function determination circuit of the ground bonding option type shown in FIG. 1.
In the case of the power supply bonding option, at the time of the non-bonding type, nMOS transistor QN1 pulls down charge from the junction C to prevent floating. Meanwhile, as well known in the art, an nMOS transistor has a current capacity of approximately twice that of a pMOS transistor if the geometrical dimensions such as channel length, channel width or gate insulating film thickness are equal between the transistors. Accordingly, if it is intended to obtain equal consumption current between function determination circuits of the power supply bonding option type and the ground bonding option type, the channel length of nMOS transistor QN1 must be set to twice the channel length of pMOS transistor QP1. In other words, the area of the transistor QN1 is approximately twice the area of the transistor QP1.
As described above, in the conventional function determination circuit shown in FIG. 1, where it is of the ground bonding type wherein the bonding pad 1 and the external grounding terminal are bonded to each other, current always flows from a power supply line 2 via transistor QP1, junction A to bonding pad 1, while current is consumed.
In order to reduce the current consumption, it is effective to provide a transistor QP1 of high resistance. In principle, the current consumption can be reduced to zero if the resistance of transistor QP1 is increased infinitely, or in other words, transistor QP1 is removed. However, if transistor QP1 is removed, then, in the case of non-bonding, the bonding pad 1 is put into a floating state. Even if a circuit is added to set the junction A to the level H when power is supplied, the junction A thereafter is put into a floating state. As a result, the voltage level at the junction A may possibly exceed the threshold level of the invertor 4A due to variation of the power supply voltage or noise produced in the LSI, resulting in reversal of output signal φ1 to the level L. That is, removal of transistor QP1 is a very risky measure since it may possibly damage the reliability of operation, and hence such measure cannot be employed in practical use.
After all, it is a realistic countermeasure to maximize the channel length of transistor QP1 so as to provide a high resistance in order to reduce the current consumption as far as possible within a range within which the function determination circuit can operate normally against a variation of the power supply voltage or noise. This countermeasure may, however, produce an effect that the area of the transistor QP1, or in other words, the area occupied by the function determination circuit increases. For example, while the current consumption of the function determination circuit is designed so as to be lower than approximately 0.5 μA, the area of transistor QP1 in this instance is as large as approximately 2,500 μm2. In recent years, in order to reduce the production cost of LSIs as much as possible, number of kinds of LSIs to be produced on the same kind of chips is in an increasing tendency, and many LSIs include a large number of function determination circuits carried on one chip. For example, in an LSI wherein six function determination circuits are carried on a chip, the total area of transistors QP1 is as large as that of one bonding pad, and as a result, the chip area is increased significantly.
Such an increase of the chip area caused by reduction in current consumption of a function determination circuit as described above makes a more serious problem with the LSI of the power supply bonding option type shown in FIG. 2. This is due to the fact that, in the case of power supply bonding option type, the current capacity of nMOS transistor QN1 employed therein is as high as approximately twice the current capacity of pMOS transistor QP1.